A non-volatile memory is a device that can retain stored information without an external power source. One way of accomplishing this is by using a field effect transistor where the controlling electric field is generated by charges trapped in the gate structure of the device. Such charge trapping sites may be formed in the gate insulator material in a variety of ways. For example, one such trap formation is accomplished by using a dual dielectric layer for the gate insulator and using the normally occurring interfacial states as traps for charges. With the application of an appropriate control voltage on the gate structure, charges from the transistor channel region tunnel through the normally thin first dielectric material and are trapped in the interfacial states. The second dielectric is made thick enough to prevent any further tunneling of the charges through it. The charges cannot tunnel back to their original position since they need the influence of an electric field of opposite polarity to the one that caused them to tunnel through the first dielectric initially. In the absence of any external field, the charges will remain trapped in their positions. This phenomenon provides the non-volatile character of the structure. While the charges remain stored in these interfacial states they provide an electric field of their own which influences the conductivity of the transistor channel. Because of the proximity of the charges to the channel, the field generated by these charges is sufficient to control the logic state of the device. Assuming a proper biasing for the drain and source regions of the transistor, the device cannot change its logic state unless and until a control voltage of opposite polarity forces the charges back into the channel and thus eliminates their control over the conductivity of the channel.
Among the most important parameters for such devices are the write and erase times, the control voltage, and the threshold voltage of the transistor. The write and erase times must be as small as possible for optimum high frequency operation. Fast writing can be accomplished by decreasing the thickness of the dielectric that the charges have to tunnel through thus increasing the tunnel current, or by increasing the density of available traps, or by introducing traps of high efficiency for capturing the tunneled charges i.e. traps with a large capture cross section. However, the dielectric must be thick enough to prevent the charges from tunneling back in the absence of any control voltage. The thickness of this dielectric is also determinative of the size of the control voltage that is required to cause a tunneling of the charges. The threshold voltage depends on the density and polarity of the stored charges and how close they are to the semiconductor interface. It is clear therefore that accurate control of the thickness of the thin dielectric layer contiguous to the silicon surface, together with accurate control of the density of charge trapping states, are the two key ingredients for a successful fabrication of non-volatile memories with reproducible electrical characteristics.